The main drawback of processors, performed under the CISC architecture, a large number of possible ways to send data, which leads to complicated operations, the use of different methods of addressing. All mikrooperatsii of CISC processors have a different format, different number of operands, as well as various times for various instructions.

Analysis of a set of instructions processors made by CISC architecture, showed that the most used programs (80%) instructions the processor accounted for only 20% of all teams CISC processors, while 80% lesser teams.
To solve the problems inherent in CISC architecture, has developed a new RISC architecture. The core computer, performed on RISC architecture, and contains a collection of the most frequently used mikrooperatsy, so at a crystal computer was made possible the deployment of more general purpose registers.

The main advantages of RISC architecture is the presence of the following characteristics:

A large number of general-purpose registers.

Universal format for all instructions.

Equal time, carry out all instructions.

Virtually all the transactions carried out by sending data along the route register - register.

These features allow teams to handle the flow of instructions on the conveyor principle, that is synchronized hardware parts, taking into account the serial control from one hardware unit to another.
Hardware blocks allocated in the RISC architecture:

Block downloading instructions includes the following components: cluster sample instructions from memory instructions, the register of instructions, where instruction is placed after the sample and block decoding instructions. This stage is called stage sampling instructions.

General-purpose registers, together with the control unit registers constitute the second stage of the conveyor responsible for reading instruction operands. Operands can be stored in the instructions or in a general-purpose registers. This stage is called the sample stage operand.

Arithmetic logic unit, along with the logic of management, which is based on the contents of the register of instructions, determines the type carried out mikrooperatsii. The data in addition to register instructions may be counter command, in carrying out mikrooperatsy conditional or unconditional move. This step is called the executive level of the conveyor.

A set of general-purpose registers, logic and sometimes record of RAM form a step storing data. At this stage the result of instructions written in general-purpose registers or in main memory.